1. Field of the Invention
This invention relates to semiconductor packages for mounting semiconductor chips using lead frames, which are attached onto circuit boards. This invention also relates to methods for manufacturing semiconductor packages using lead frames.
This application claims priority on Japanese Patent Application No. 2003-99126 and Japanese Patent Application (not yet assigned a number, which claims priority on Japanese Patent Application No. 2003-99126 in Japan), the contents of which are incorporated herein by reference.
2. Description of the Related Art
Conventionally, leads frames are used for semiconductor packages incorporating semiconductor chips. A typical example of the lead frame for use in the conventionally-known semiconductor package is shown in FIG. 13, wherein a lead frame 51 comprises a stage 55 for mounting a semiconductor chip 53, a plurality of leads 57 arranged in the periphery of the stage 55, and dam bars 59 for interconnecting the leads 57. This lead frame 51 is manufactured by performing press working or etching process on a thin metal plate.
The aforementioned lead frame 51 can be used for manufacturing the conventionally-known semiconductor package of a QFN type (i.e., a Quad Flat Non-Leaded package), for example. In this case, the semiconductor chip 53 is bonded onto the surface of the stage 55, wherein pads thereof are electrically connected with the leads 57 via bonding wires 61. Then, as shown in FIG. 14, a molded resin 63 is formed to integrally fix the semiconductor chip 53, the stage 55, the bonding wire 61, and the bonding portion of the lead 57 together. Herein, a backside 57a of the lead 57 forms the same plane together with a backside 63a of the molded resin 63.
A prescribed surface 57b of the lead 57 is exposed to the exterior of the molded resin 63 and is subjected to plating together with the backside 57a of the lead 57, whereby plated films 65 are formed thereon in order to improve solder wettability with respect to the lead 57.
Thereafter, a projecting portion 57c of the lead 57, which projects outwardly from the molded resin 63, is cut out together with a dam bar 59 at a cutting line A, so that the leads 57 are made electrically independent of each other, thus completing the production of the semiconductor package.
The conventionally-known package of a QFP type (i.e., a Quad FlatPack package) is designed such that plated films are formed on the surface and backside of the projecting portion of the lead as well as the adjacent side areas of the leads in order to improve the wettability, wherein the solder is adhered not only to the backside of the lead but also to the side area and surface of the lead.
In the QFP package, the projecting portion of the lead is subjected to half etching so as to form a thinned portion, thus increasing the overall solder adhesion area of the lead, an example of which is disclosed in Japanese Patent No. 3008470.
In the QFN package shown in FIG. 14, the lead 57 is cut out at the cutting line A, whereby a cut surface 57d of the lead 57 lying in the thickness direction is not accompanied with a plating film 65 as shown in FIG. 15, whereas other surfaces of the lead 57 except the cut surface 57d are covered with the molded resin 63 so that they do not join with a solder 67. That is, when a semiconductor package 80 is attached onto a circuit board 71 via the solder 67 as shown in FIG. 15, only a land portion 73 of the circuit board 71 is electrically connected with the backside 57a of the lead 57. This causes difficulty in inspecting the joined state established between the solder 67 and the lead 57 through visual inspection. Hence, there is a problem in that reliability secured for the electrical connection established between the semiconductor package 80 and the circuit board 71 may be reduced.
The aforementioned Japanese patent discloses a method for increasing the overall solder adhesion area with respect to the leads. However, in the QFN package in which the lead 57 is not substantially projected outside of the molded resin 63 so that the other surfaces of the lead 57 adjoining the cut surface 57d are covered with the molded resin 63, this method cannot contribute to enhancement of the joining strength established between the cut surface 57d of the lead and the solder 67; that is, it cannot solve the aforementioned problem.